A photovoltaic structure generates electrical power by converting light into direct current electricity using semiconductor materials that exhibit the photovoltaic effect. The photovoltaic effect generates electrical power upon exposure to light as photons, packets of energy, are absorbed within the semiconductor to excite electrons to a higher energy state, leaving behind an empty state (“hole”). These excited electrons and holes are thus able to conduct and move freely within the material.
A basic unit of photovoltaic structure, commonly called a cell, may generate only small scale electrical power. Thus, multiple cells may be electrically connected to aggregate the total power generated among the multiple cells within a larger integrated device, called a module, or a panel. A photovoltaic module may further comprise a protective back layer and encapsulant materials to protect the included cells from environmental factors. Multiple photovoltaic modules or panels can be assembled together to create a photovoltaic system, or array, capable of generating significant electrical power up to levels comparable to other types of utility-scale power plants. In addition to photovoltaic modules, a utility-scale array would further include mounting structures, electrical equipment including inverters, transformers, and other control systems. Considering various levels of device, from individual cell to utility-scale arrays containing a multitude of modules, all such implementations of the photovoltaic effect may contain one or more photovoltaic structures to accomplish the energy conversion.
To generate power from sunlight, the active area of a photovoltaic structure or device generally includes a bi-layer of two distinct regions, one above the other and each containing one or more materials, where each material may further contain added impurities. The result is that one region in the photovoltaic device is n-type, having an excess of negatively charged electrons, while the other is p-type, having an excess of positively charged holes. These regions are commonly named the window layer, for the n-type region, and the absorber layer, for the p-type region. Where these two regions abut one another, a p-n junction is formed. The window layer is preferred to be as thin as possible in order to allow the maximum amount of light to reach the absorber layer, yet it also needs to be sufficiently thick to maintain a robust p-n junction with the absorber layer.
When photons create free electrons and holes, collectively called charge carriers, near the p-n junction, the internal electric field of the junction causes the electrons to move towards the n side of the junction and the holes towards the p side thereby generating an electrical charge potential. A front contact, electrically connected to the window layer, and a back contact, electrically connected to the absorber layer can provide pathways through which the electrical charge potential can flow to become an electrical current. Electrons can flow back to the p-side via an external current path, or circuit.
While moving within the material where generated mobile electrons and holes may recombine due to the presence of recombination centers such as point defects or structural defects, including grain boundaries and material interfaces. This reduces the total number of charge carriers available to generate current flow within the device and the overall conversion efficiency. Efficiency, in this instance, refers to the electrical power or energy generated by the PV device compared to the equivalent energy of photons incident on the device.
The manufacturing of a photovoltaic structure generally includes sequentially forming the functional layers through process that may include vapor transport deposition, atomic layer deposition, chemical bath deposition, sputtering, closed space sublimation, or any other suitable process that creates the desired material. Once a layer is formed it may be desirable to modify the physical characteristics of the layer through subsequent activation processes. For example, an activation step may include passivation, which is defect repair of the crystalline grain structure, and may further include annealing. Imperfections or defects in the crystalline grain disrupt the periodic structure in the layer and can create areas of high resistance or current loss.
An activation process may accomplish passivation or structural or point defects through the introduction of a chemical dopant to the semiconductor bi-layer as a bathing solution, spray, or vapor. Subsequently annealing the layer in the presence of the chemical dopant at an elevated temperature provides grain growth and incorporation of the dopant into the layer. The larger grain size reduces the resistivity of the layer, allowing the charge carriers to flow more efficiently. The incorporation of a chemical dopant may also make the regions of the bi-layer more n-type or more p-type and able to generate higher quantities of mobile charge carriers. Each of these improves efficiency by increasing the maximum voltage the device can produce and reducing unwanted recombination.
In the above activation process, the summary parameters of anneal temperature, chemical bath composition, and soak time, for a particular layer depend on that layer's material and may have adverse effects on other layers present in the photovoltaic structure. For example, during the activation step of the absorber layer, the high temperature anneal may cause the window layer to flux into and intermix with the absorber layer, which can lead to the window layer having a non-uniform thickness or becoming discontinuous, which decreases device performance. It would be desirable to use more chemically potent doping solution, higher annealing temperatures, or longer anneal duration in an activation step to more aggressively treat the absorber layer, as this would increase the benefits conferred on the absorber layer by the activation step. However, using more aggressive process conditions during the activation step can cause more fluxing, thus further degrading or destroying the window layer, which decreases device performance. Alternatively, the TCO may perform the function of the n-type layer. In this case, the constraints of annealing are imposed by film defects at the interface of the TCO and the absorber that may increase recombination.
This problem cannot be solved by simply increasing the initial thickness of the window layer so that if some of the material is fluxed away during the activation step, enough remains to maintain a good junction. This apparent remedy causes other problems as the window layer will absorb some photons and having a thicker window layer after the activation step reduces the available light for photon harvesting at the absorber layer. In general, it may be desired to have a very thin window layer to provide better light transmission to the absorber layer. One method to form very thin windows but allow for aggressive annealing is to interpose an alloy layer to retard the interdiffusion. An example would be to use a CdS/CdSxTe1−x/CdTe structure. In this case the ternary alloy layer reduces the concentration gradient in S and thus retards the interdiffusion flux.
Bi-layer semiconductor stacks, such as those having CdSe/CdTe layers, require inter-diffusion to form the desired composition alloy for increased infrared photon absorption. The optimum final Se profile may not be best achieved from the inter-diffusion from a starting bi-layer structure. In this case inter-diffusion from a CdSe/CdSexTe1−x/CdTe tri-layer starting structure can be used to craft a desired final Se profile. For bi-layers and tri-layers, the initial CdSe seed layer is usually not present in the final structure but rather serves as a Se source leading to a graded Se composition within a CdSexTe1−x layer.
Devices with CdSexTe1−x as an alloy absorber are typically made by depositing a layer of CdSe or CdSexTe1−x ternary with a high Se mole fraction x, followed by a layer of CdTe and/or CdSexTe1−x with a low Se mole fraction. During a subsequent cadmium chloride treatment, the layers are intermixed creating a smooth continuous Se profile in the device. Peak Se concentration in these devices is located at the interface between the device absorber and the TCO.
Therefore, it is desirable to provide an efficient p-n junction between layers of semiconductor materials, incorporating an absorber layer that can be activated with an aggressive activation step.